The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and designs have produced generations of ICs each having smaller and more complex circuits. In the course of IC evaluation, the geometry size or technology node (e.g., smallest component or line that can be imaged) has decreased. Shrinking technology nodes generally provide benefits by increasing production efficiency and lowering costs. However, these advances have also increased the complexity of fabricating of the circuits. For example, the scaling-down feature sizes can lead to fabrication challenges such as meeting process overlay margins. As the technology nodes shrink, the process overlay margins also shrink—and become more and more critical. One such process where the layout of the device demands alignment of closely-spaced features is in the fabrication of interconnect structures for the IC device. Thus, advances in IC fabrication are needed.